Week 4.a
CS6640
09/26 2023
https://naizhengtan.github.io/23fall/

1. Timer interrupt overview
2. Register interrupt handler
3. Periodical timer interrupt
4. Enabling timer
5. Interrupt in egos-2k+
----

Admin:
  -- survey (during Q&A)

  Roadmap of lab2--lab4

  [basic RISC-V CPU] non-preemptive multi-threading  (lab2)
  [+ timer interrupt] preemptive scheduling          (lab3)
  [+ privilege levels] memory protection and syscall (lab4)

1. Timer interrupt

    two views:
      -- from a CPU's perspective
         [see slides]
      -- from a programmer's perspective

    """
    void handler() {
        CRITICAL("Got a timer interrupt!");
        // (4) reset timer
    }

    int main() {
        CRITICAL("This is a simple timer example");
        // (1) register handler() as interrupt handler
        // (2) set a timer
        // (3) enable timer interrupt

        while(1);
    }
    """


2. Interrupt handler

  Q: How to register handler() as interrupt handler?

  Q: if you were CPU designer, how would you like to define the interface?

  In RISC-V,
  the answer is mtvec, a control and status registers (CSR)
  [see examples]

  Background: RISC-V assembly II

    asm(Template : OutputOperands : InputOperands)

    a) Template: a string that is the template for the assembler code.

        asm("mret");

    b) OutputOperands: the C variables modified by the instructions 
       in the Template.

        void *sp;
        asm("mv %0, sp" : "=r"(sp));

    c) InputOperands: C expressions read by the instructions in the Template.

        int mie;
        asm("csrr %0, mie" : "=r"(mie));
        asm("csrw mie, %0" ::"r"(mie | 0x80));


    [if you want to know more, gcc doc: 
      https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html]


3. Periodical timer interrupt

  Q: how to set the timer such that there will be a timer interrupt in a
     expected period of time?
  [see examples]


4. Enable timer

  Q: How to enable timer interrupt?
  [see examples]


[skipped]
5. Interrupt in egos-2k+

  [Exploration: where is the interrupt handler in egos-2k+?]
  * in gdb, by "p/x $mtvec"; we will see mtvec = 0x20400200
  * by checking the memory layout, we found it is in earth
  * by checking build/debug/earth.lst, we see the handler named "trap_entry"
  * by grep, we see the code in "earth/cpu_intr.c"

  Privilege mode vs. interrupt handler
  [see earth/cpu_intr.c]