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References and Materials

OSI

  • RISC-V instruction listings (pdf)
  • RISC-V registers (pdf)
  • RISC-V trap reason table (pdf)
  • RISC-V calling convention (pdf)

egos-2k+

  • egos-2k+ architecture (pdf)
  • egos-2k+ memory layout (pdf, text)
  • egos-2k+ syscall workflow (text)
  • egos-2k+ qemu-emulated CPU memory map (pdf)
  • diff between egos-2k+ and egos-2000 (html)

C language

  • C operator precedence and associativity (pdf, html)

RISC-V specs

QEMU and SiFive CPU

  • QEMU docs
  • SiFive FE310 SoC
    • note: for egos-2k+, the “Chapter 4: memory map” is inaccurate, as we use a qemu-emulated CPU. See “egos-2k+ qemu-emulated CPU memory map” above.

OS basics