Week 4
CS4973/CS6640
01/27 2025
https://naizhengtan.github.io/25spring/

□ 1. Timer interrupt
□ 2. Review: OS scheduling
□ 3. egos scheduler & lab3
---

1. Timer interrupt

  A. Basic concept

    * Timer interrupt in two views:

     1. from a CPU's perspective
      [see slides]

     2. from a programmer's perspective

      Q: as a programmer, have you ever programmed interrupts?

      [see handout panel 1]
      """
      void handler() {
          CRITICAL("Got a timer interrupt!");
          // (4) reset timer
      }

      int main() {
          CRITICAL("This is a simple timer example");
          // (1) register handler() as interrupt handler
          // (2) set a timer
          // (3) enable timer interrupt

          while(1);
      }
      """

  B. Interrupt handler

    Q: How to register handler() as interrupt handler?

    Q: if you were CPU designer, how would you like to define the interface?

    In RISC-V,
    the answer is mtvec, a control and status registers (CSR)
      [see slides]

    ---
    Background: RISC-V assembly II

      asm(Template : OutputOperands : InputOperands)

      a) Template: a string that is the template for the assembler code.

          asm("mret");

      b) OutputOperands: the C variables modified by the instructions 
         in the Template.

          void *sp;
          asm("mv %0, sp" : "=r"(sp));

      c) InputOperands: C expressions read by the instructions in the Template.

          int mie;
          asm("csrr %0, mie" : "=r"(mie));
          asm("csrw mie, %0" ::"r"(mie | 0x80));

      [if you want to know more, gcc doc: 
        https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html]
    ---

  C. Periodical timer interrupt

    Q: How can the timer be configured to generate an interrupt after a
    specified period of time?

    Q (open-ended): If you were a CPU designer, how would you design the
    interface for this functionality?

  D. Enable timer

    Q: How to enable timer interrupt?


  E. Recap: RISC-V timer interrupt
    (1) register handlers
    (2) set timer
    (3) enable timer interrupt
    We will see where egos does these.

  CPU provides a set of registers: 
    'mtvec',  'mstatus', 'mie', 'mtime', 'mtimecmp'

    Q: what is "static variable" in C?

  ---
  [skipped]
  Demo: Interrupt in egos-2k+

  [Exploration: where is the interrupt handler in egos-2k+?]
  * in gdb, by "p/x $mtvec"; we will see mtvec = 0x20400200
  * by checking the memory layout, we found it is in earth
  * by checking build/debug/earth.lst, we see the handler named "trap_entry"
  * by grep, we see the code in "earth/cpu_intr.c"

  Privilege mode vs. interrupt handler
  [see earth/cpu_intr.c]
  ---

2. Review: OS scheduling

    High-level problem: operating system has to decide which process
    (or thread) to run.

    A. When scheduling decisions happen:

        [show process transition diagram]

                                                 exit (iv)
    [loading]                                   +-------->[unused]
     |                     (iii) interrupt      |
     +->[ready/runnable]  <--------------    [running]
                  ^       --------------->      |
      syscall msg  \      scheduler dispatch    |
   or wake up (ii)  \                 __________|
                     \               /
                     ["waiting"] <--/ syscall or sleep (i)


    Scheduling decisions take place when a process:

      (i) Switches from running to waiting state 
      (ii) Switches from waiting to ready 
      (iii) Switches from running to ready state 
      (iv) Exits 

    Preemptive scheduling: at all four points

    Nonpreemptive scheduling: at points (i), (iv), only (this is the
    definition of nonpreemptive scheduling)


    B. what are the metrics and criteria?

    timeline ----v---------v-------v------v-----v---->
              arrival  1st exec  yield   2nd  completion

    --turnaround time
    time for each process to complete (completion - arrival)

    --waiting/response/output time. variations on this definition,
    but they all capture the time spent waiting for something to
    happen rather than the time from launch to exit.

        --time between when job enters system and starts executing;
        following the class's textbook, we will call this "response time"
        (1st execution - arrival)
        [some texts call this "waiting time"]

    --CPU time: how much CPU time the process actually consumed
       (this is the time when pc points to the code of this process)


3. egos scheduler

  A. Processes in egos (sifive_e)

   * Process control block in egos-2k+
      [see handout]

   * Process life cycle in egos-2k+
      [see handout]

   [skipped]
   * Calculating scheduling metrics

    Q: how to calculate turnaround time?

    Q: how to calculate response time?

    Q: will timer overflow in egos?
      [Demo]


  B. Kernel scheduler

   a) Now
      [read grass/scheduler.c]

      Try "loop &" and "ls", which is super slow.

      Q: why this is the case?
      Because the loop which runs for a long time has the same priority as
      system services and short-lived jobs, so it takes at least one QUANTUM
      to hear back from system service.

   b) Multi-level feedback queue
      [a brief intro; see OSTEP Ch8]

  C. Lab3 misc

   -- C: union
      a composite data type that allows you to store different types of data in
      the same memory location. This is useful for data that can be interpreted
      as multiple types.

      Q: what does the code print?

      """
      union tmp {
        int  num;
        char chars[4];
      };

      union tmp u = {0};
      u.num = 0x41; // ascii, 'A'
      printf("%s\n", u.chars);
      """

      Q: what about these:

      """
      u.num = (0x41 << 8); // ascii, 'A'
      """
      should get nothing, because the string starts with "\0".

      """
      u.num = (0x41 << 8) + 0x42; // ascii, 'A'
      """
      should get "BA", because of little-endian.