References and Materials

OSI

• RISC-V instruction listings (pdf)
• RISC-V registers (pdf)
• RISC-V trap reason table (pdf)
• RISC-V calling convention (pdf)

egos-2k+ (sifive_e)

• egos-2k+ qemu-emulated sifive_e CPU memory (pdf)

C language

• C operator precedence and associativity (pdf, html)

RISC-V specs

• The RISC-V Reader: An open architecture atlas by D. Patterson and A. Waterman, Strawberry Canyon, 2017.
• RISC-V Unprivileged Instruction Set Manual
• RISC-V Privileged Instruction Set Manual

QEMU and SiFive CPU

• QEMU docs
• SiFive FE310 SoC
  • note: for egos-2k+, the “Chapter 4: memory map” is inaccurate, as we use a qemu-emulated CPU. See “egos-2k+ qemu-emulated CPU memory map” above.

OS basics

• OSTEP: Operating Systems: Three Easy Pieces, by Remzi H. Arpaci-Dusseau and Andrea C. Arpaci-Dusseau, August 2018, edition 1.00.