Week 4.b
CS6640
01/30 2026
https://naizhengtan.github.io/26spring/

□ 1. egos-2k+ booting process
□ 2. RISC-V assembly in C
□ 3. Timer interrupt
----

1. egos-2k+ booting process

  The botting process:
    [see handout from last time, panel 2]

  Q: why did a process finish already?
     Will see when we go through the entire process.
    [answer: see apps/system/sys_shell.c]

  Q: use gdb to trace the booting

  [see handout, panel 3]
  CPU jmps to 0x80000000
   |
   +-> earth/boot.s:boot_loader
       |
       +-> earth/boot.c:boot
           |
           +-> grass/init.c:grass_entry
               |
               +-> grass.c:main
                   |
                   +-> ['mret' to APPS_ENTRY]
                       |
                       +-> apps/system/sys_proc.c:main
                           |
                           ...
                           |
                           +-> apps/system/sys_shell.c:main


  * in earth/boot.c

    Q: what does asm("csrr %0, mhartid" : "=r"(core_id)) do?
    [A: on RISC-V manual:
        (1) read "csrrc"
        (2) read "mhartid"]

  * in grass/init.c

    Q: Does it work to directly jump to APP_ENTRY? (instead of using 'mret')
    [Answer: it works, but the privilege level will be different]

  * in sys_shell.c

    Q: why a process died?
    [Answer: that's "cd"]

2. RISC-V assembly in C

      asm(Template : OutputOperands : InputOperands)

      a) Template: a string that is the template for the assembler code.

          asm("lw ra,12(sp)");
          asm("ret");

          Q: Why do we need "lw"?
          A: to restore the return value

      b) OutputOperands: the C variables modified by the instructions 
         in the Template.

          void *sp;
          asm("mv %0, sp" : "=r"(sp));

      c) InputOperands: C expressions read by the instructions in the Template.

          void *sp = (void*)0x803fffc0;
          asm("mv sp,%0" :: "r"(sp));

      [go through examples]
      Q: for each example, ask students what to expect.

      [if you want to know more, gcc doc: 
        https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html]

3. Timer interrupt

    two views:
      -- from a CPU's perspective
         [see slides]
      -- from a programmer's perspective

    [uncomment functions in earth/boot.c]
    [see grass/week4b_timer.c]

    """
    void handler() {
        CRITICAL("Got a timer interrupt!");
        // (4) reset timer
    }

    int main() {
        CRITICAL("This is a simple timer example");
        // (1) register handler() as interrupt handler
        // (2) set a timer
        // (3) enable timer interrupt

        while(1);
    }
    """

  A) hardware interrupt handler

    Q: How to register handler() as interrupt handler?

    Q: if you were CPU designer, how would you like to define the interface?
       For example, creating a dedicated instruction?

       So...what are the CPU interfaces?
       - instructions
       - registers
       - speical memory addresses
       - exceptions

    In RISC-V,
    the answer is mtvec, a control and status registers (CSR)
      [see slides]


  B) Periodical timer interrupt

    Q: how to set the timer such that there will be a timer interrupt in a
       expected period of time?

    Q: if you were CPU designer, how are you going to design the interface?


  C) Enable timer

    Q: How to enable timer interrupt?